Ting-Chou (James) Lin

Advanced Micro Devices, Inc

Software Engineer • Apr, 2023 — Present

• AMD AI Engine Compiler Team - developed C++ graph compiler tools for ML models targeting AMD AI Engine processors
• Designed reference kernels using internal C++ graph representation and enhanced features to address customer concerns (C++)
• Engineered an MLIR-based compiler lowering pipeline that generates C++ graph code, which is then integrated into the existing C++ graph compiler flow (MLIR)

Cerebras Systems, Inc

Software Engineer • May, 2019 — Feb, 2023

Cerebras offers the fastest AI accelerator, based on the largest processor in the industry.

• Cerebras Graph Compiler Team -- developed algorithms that transform a computational graph representation of large language and vision models to a specific performance-optimized running plan for the Cerebras hardware AI accelerators
• Collaborated cross-functionally with ML model, framework, and kernel teams to resolve challenging compiler issues and led the efforts to enable the use of BERT NLP models on the Cerebras hardware AI accelerators
• Investigated various methods for kernel placement and routing, resulting in a 15% reduction in compile time for large language and vision models in the Cerebras Graph Compiler (C++)
• Implemented compiler lowering paths for internal graph representation of large language and vision models and achieved comprehensive unit test coverage for the neural network operations in the internal graph representation (MLIR/Python)

Cadence Design Systems, Inc

Software Engineer • Oct, 2017 — Mar, 2019

Cadence is a leading EDA provider delivering software for electronic design.

• Developed two commercial tools, SiP (C++) and OrbitIO (Java), in collaboration with teams in Taiwan, U.S., and China to implement Taiwan Semiconductor (TSMC)’s certificated reference development flows and features for global customers
• Enhanced algorithms in pivotal features of SiP, resulting in 40x/10x speedups, decreasing runtime from days to hours
• Implemented regression tests in shell scripts Bash, ensuring a streamlined approach for continuous integration and delivery

The OpenROAD Project

Research Assistant • May, 2019 — Aug, 2020

• 24-hour, No-Human-In-The-Loop layout design for SOC, Package and PCB
• Machine-learning-driven parallel search and optimization
• Focused on a multi-objective cost-driven path finding problem with complex constraints
• Main developer of the open source PCB Router
• Published one research paper in IEEE/ACM ASP-DAC 2021

Joint Research Project, AnaGlobe

Internship, Software Engineer • Sep, 2016 — Aug, 2017

• Focused on RDL routing for TSMC InFO_PoP advanced packaging technologies
• Proposed to transform a routing sequence into two directed acyclic graphs to minimize multiple objectives
• Experimental results showed that our router can achieve 100% routablility for all given test cases
• Published two research papers in IEEE/ACM ICCAD 2016 & 2017, and a US Patent, US 2018/0032660 A1

Programing Languages

C/C++, Python, Java, Go

Skills & Framework

PyTorch, TensorFlow, MLIR, Git, Perforce, Docker, SQL, JenkinsCI/CD, Valgrind, gdb

Review and Extension of AlphaNPI @ NeurIPS'19

Winter, 2020

• Original paper is available at Learning Compositional Neural Programs with Recursive Tree Search and Planning
• Studied the AlphaZero reinforcement learning algorithm and Neural Programmer-Interpreters (NPI)
• Implemented an extension to show that a single core LSTM is capable of learning multiple programs

Drug Rating Prediction of the Drug Review Dataset

Fall, 2019

• Dataset is available at UCI Machine Learning Repository
• Mixed uni- & bi-gram words with TF-IDF as features to represent drug review text
• Adopted random forest regressor to achieve R^2 with 0.79 when predicting drug rating

University of California, San Diego

Master of Science • 2019 — 2021

• Major - Computer Science and Engineering (Overall GPA 3.97/4.00)
• UCSD Fellowship and Graduate Student Researcher
• UCSD J. Yang Scholarship Award

National Taiwan University

Master of Science • 2015 — 2017

• Major - Electronics Engineering (Overall GPA 4.23/4.30)
• NTU Academic Scholarship Award (two times)

Koç University

Undergraduate Exchange Student • 2015

National Chiao Tung University

Bachelor of Science • 2011 — 2015

• Major - Electronics Engineering (Overall GPA 4.02/4.30)
• Minor - Computer Science
• NCTU Academic Scholarship Award

T.-C. Lin, D. Merrill and Y.-Y. Wu, C. Holtz, and C.-K. Cheng “A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2021 (to appear)

T.-C. Lin, C.-C. Chi, and Y.-W. Chang, “Redistribution Layer Routing for Wafer-Level Integrated Fan-Out Package-on-Packages,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2017 (acceptance rate: 105/399=26%)

B.-Q. Lin, T.-C. Lin, and Y.-W. Chang, “Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Package,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016 (acceptance rate: 97/409=24%)

B.-Q. Lin, T.-C. Lin, C.-Y. Yang, and Y.-W. Chang, “Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages,” US Patent US 2018/0032660 A1, Feb. 2018